1. Field of the Invention
The present invention relates to a frequency multiplier circuit that achieves a desired frequency by multiplying the frequency of a reference clock.
2. Description of the Related Art
A frequency multiplier circuit in the prior art comprises a PLL (phase-locked loop) circuit, a frequency divider circuit and the like. In the prior art, a signal indicating a phase difference between a feedback clock and a reference clock is converted to an analog voltage by using a charge pump and a low pass filter inside the PLL circuit and a desired frequency is achieved by controlling a voltage-controlled oscillator in the PLL circuit with the analog voltage.
However, the following problem arises in a frequency multiplier circuit employing the PLL circuit in the prior art.
Since the PLL circuit includes an analog circuit, the inconsistency in the manufacturing process and the operating conditions such as source voltage fluctuations or operating temperature greatly affect the characteristics of the PLL circuit. For this reason, the desired frequency may not be always achieved.
In order to address the problem discussed above, the frequency multiplier circuit that outputs a frequency achieved by multiplying the frequency of a reference clock in a first invention assumes the following structure.
Namely, the frequency multiplier circuit comprises a first frequency divider that divides the frequency of the reference clock by 4, a second frequency divider that divides the frequency of the unit clock, which is higher than the frequency of the reference clock by 2, an AND means that obtains the AND of an output signal from the first frequency divider and an output signal from the second frequency divider, a first variable frequency divider that divides an output signal from the AND means by n using variable frequency division data n (n is a positive integer) provided from the outside, an up-counter that counts the number of pulses Y in an output signal from the first variable frequency divider over intervals each corresponding to a half cycle of the output signal from the first frequency divider and a second variable frequency divider that divides the frequency of the unit clock by Y by taking in the number of pulses Y obtained through the count as frequency division data and outputs a signal achieved by multiplying the frequency of the reference clock by n.
By adopting the structure described above, the AND of the output signals from the first frequency divider and the second frequency divider is calculated by the AND means and then the AND is divided by n by the first variable frequency divider. The number of pulses Y in the output signal from the first variable frequency divider is counted by the up-counter over intervals each corresponding to a half cycle of the output signal from the first frequency divider. The second variable frequency divider divides the frequency of the unit clock by the number of pulses Y and a signal with a frequency achieved by multiplying the frequency of the reference clock by n is obtained. In other words, the frequency multiplier circuit is achieved without using any analog circuit components that are affected by inconsistencies in the manufacturing process and the operating conditions.
In a second invention, a third variable frequency divider described below is provided in the frequency multiplier circuit in the first invention.
The third variable frequency divider, which is connected to either the input side or the output side of the first frequency divider, operates in conjunction with the first frequency divider to divide the frequency of the reference clock by (4xc3x97m) using variable frequency division data m (m is a positive integer) provided from the outside and to provide the results of the frequency division to the AND means.
In this structure, the number of pulses Y counted by the up-counter in the first invention is multiplied by m.
In a third invention, the first frequency divider, the second frequency divider, the AND means, the first variable frequency divider, the up-counter and the second variable frequency divider in the frequency multiplier circuit in the first invention are formed at a common board at which an internal oscillator that generates the unit clock is formed.
In this structure, the unit clock is internally generated by the internal oscillator. The process conditions and the operating conditions of the internal oscillator can be matched with those of the other circuits.
In a fourth invention, the first frequency divider, the second frequency divider, the AND means, the first variable frequency divider, the up-counter, the second variable frequency divider and the third frequency divider in the frequency multiplier circuit in the second invention are formed at a common board at which an internal oscillator that generates the unit clock is formed.
In this structure, the unit clock is internally generated by the internal oscillator and the process conditions and the operating conditions of the internal oscillator can be matched with those of the other circuits.